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xr-2211 ...the analog plus company tm fsk demodulator/ tone decoder rev. 3.01 1992 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 1 june 1997-3 features wide frequency range, 0.01hz to 300khz wide supply voltage range, 4.5v to 20v hcmos/ttl/logic compatibility fsk demodulation, with carrier detection wide dynamic range, 10mv to 3v rms adjustable tracking range, + 1% to 80% excellent temp. stability, + 50ppm/ c, max. applications caller identification delivery fsk demodulation data synchronization tone decoding fm detection carrier detection general description the xr-2211 is a monolithic phase-locked loop (pll) system especially designed for data communications applications. it is particularly suited for fsk modem applications. it operates over a wide supply voltage range of 4.5 to 20v and a wide frequency range of 0.01hz to 300khz. it can accommodate analog signals between 10mv and 3v, and can interface with conventional dtl, ttl, and ecl logic families. the circuit consists of a basic pll for tracking an input signal within the pass band, a quadrature phase detector which provides carrier detection, and an fsk voltage comparator which provides fsk demodulation. external components are used to independently set center frequency, bandwidth, and output delay. an internal voltage reference proportional to the power supply is provided at an output pin. the xr-2211 is available in 14 pin packages specified for military and industrial temperature ranges. ordering information part no. package operating temperature range xr-2211m 14 pin cdip (0.300o) -55 c to +125 c xr-2211n 14 pin cdip (0.300o) -40 c to +85 c xr-2211p 14 pin pdip (0.300o) -40 c to +85 c xr-2211id 14 lead soic (jedec, 0.150o) -40 c to +85 c
xr-2211 2 rev. 3.01 inp tim c1 tim c2 tim r v ref comp i 9 nc 1 v cc 4 gnd 2 3 ldf 11 ldo 6 ldoq 5 ldoqn 14 13 12 10 8 7 do pre amplifier lock detect comparator loop -det internal reference v ref fsk comp quad -det vco figure 1. xr-2211 block diagram block diagram
xr-2211 3 rev. 3.01 pin configuration v cc 14 lead cdip, pdip (0.300o) tim c1 tim c2 tim r ldo v ref nc comp i inp ldf gnd ldoqn ldoq do 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 lead soic (jedec, 0.150o) 14 1 2 3 4 5 6 7 13 12 11 10 9 8 v cc inp ldf gnd ldoqn ldoq do tim c1 tim c2 tim r ldo v ref nc comp i pin description pin # symbol type description 1 v cc positive power supply. 2 inp i receive analog input. 3 ldf o lock detect filter. 4 gnd ground pin. 5 ldoqn o lock detect output not. this output will be low if the vco is in the capture range. 6 ldoq o lock detect output. this output will be high if the vco is in the capture range. 7 do o data output. decoded fsk output. 8 comp i i fsk comparator input. 9 nc not connected. 10 v ref o internal voltage reference. the value of v ref is v cc /2 - 650mv. 11 ldo o loop detect output. this output provides the result of the quadrature phase detection. 12 tim r i timing resistor input. this pin connects to the timing resistor of the vco. 13 tim c2 i timing capacitor input. the timing capacitor connects between this pin and pin 14. 14 tim c1 i timing capacitor input. the timing capacitor connects between this pin and pin 13.
xr-2211 4 rev. 3.01 electrical characteristics test conditions: v cc = 12v, t a = +25 c, r o = 30k , c o = 0.033 f, unless otherwise specified. parameter min. typ. max. unit conditions general supply voltage 4.5 20 v supply current 4 7 ma r 0 > 10k . see figure 4. oscillator section frequency accuracy + 1 + 3 % deviation from f o = 1/r 0 c 0 frequency stability temperature + 20 + 50 ppm/ c see figure 8. power supply 0.05 0.5 %/v v cc = 12 + 1v. see figure 7. 0.2 %/v v cc = + 5v. see figure 7. upper frequency limit 100 300 khz r 0 = 8.2k , c 0 = 400pf lowest practical operating frequency 0.01 hz r 0 = 2m , c 0 = 50 f timing resistor, r 0 - see figure 5 operating range 5 2000 k recommended range 5 k see figure 7 and figure 8. loop phase dectector section peak output current + 150 + 200 + 300 a measured at pin 11 output offset current 1 a output impedance 1 m maximum swing + 4 + 5 v referenced to pin 10 quadrature phase detector measured at pin 3 peak output current 100 300 a output impedance 1 m maximum swing 11 v pp input preampt section measured at pin 2 input impedance 20 k input signal voltage required to cause limiting 2 10 mv rms notes parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production. bold face parameters are covered by production test and guaranteed over operating temperature range.
xr-2211 5 rev. 3.01 dc electrical characteristics (cont'd) test conditions: v cc = 12v, t a = +25 c, r o = 30k , c o = 0.033 f, unless otherwise specified. parameter min. typ. max. unit conditions voltage comparator section input impedance 2 m measured at pins 3 and 8 input bias current 100 na voltage gain 55 70 db r l = 5.1k output voltage low 300 500 mv i c = 3ma output leakage current 0.01 10 a v o = 20v internal reference voltage level 4.9 5.3 5.7 v measured at pin 10 output impedance 100 ac small signal maximum source current 80 a notes parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production. bold face parameters are covered by production test and guaranteed over operating temperature range. specifications are subject to change without notice absolute maximum ratings power supply 20v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input signal level 3v rms . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 900mw . . . . . . . . . . . . . . . . . . . . . . . package power dissipation ratings cdip 750mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . derate above t a = 25 c 8mw/ c . . . . . . . . . . . . . . . pdip 800mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . derate above t a = 25 c 60mw/ c . . . . . . . . . . . . . . soic 390mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . derate above t a = 25 c 5mw/ c . . . . . . . . . . . . . . . system description the main pll within the xr-2211 is constructed from an input preamplifier, analog multiplier used as a phase detector and a precision voltage controlled oscillator (vco). the preamplifier is used as a limiter such that input signals above typically 10mv rms are amplified to a constant high level signal. the multiplying-type phase detector acts as a digital exclusive or gate. its output (unfiltered) produces sum and difference frequencies of the input and the vco output. the vco is actually a current controlled oscillator with its normal input current (f o ) set by a resistor (r 0 ) to ground and its driving current with a resistor (r 1 ) from the phase detector. the output of the phase detector produces sum and difference of the input and the vco frequencies (internally connected). when in lock, these frequencies are f in + f vco (2 times f in when in lock) and f in - f vco (0hz when lock). by adding a capacitor to the phase detector output, the 2 times f in component is reduced, leaving a dc voltage that represents the phase difference between the two frequencies. this closes the loop and allows the vco to track the input frequency. the fsk comparator is used to determine if the vco is driven above or below the center frequency (fsk comparator). this will produce both active high and active low outputs to indicate when the main pll is in lock (quadrature phase detector and lock detector comparator).
xr-2211 6 rev. 3.01 principles of operation signal input (pin 2): signal is ac coupled to this terminal. the internal impedance at pin 2 is 20k . recommended input signal level is in the range of 10mv rms to 3v rms. quadrature phase detector output (pin 3): this is the high impedance output of quadrature phase detector and is internally connected to the input of lock detect voltage comparator. in tone detection applications, pin 3 is connected to ground through a parallel combination of r d and c d (see figure 3 ) to eliminate the chatter at lock detect outputs. if the tone detect section is not used, pin 3 can be left open. lock detect output, q (pin 6): the output at pin 6 is at alowo state when the pll is out of lock and goes to ahigho state when the pll is locked. it is an open collector type output and requires a pull-up resistor, r l , to v cc for proper operation. at alowo state, it can sink up to 5ma of load current. lock detect complement, (pin 5): the output at pin 5 is the logic complement of the lock detect output at pin 6. this output is also an open collector type stage which can sink 5ma of load current at low or aono state. fsk data output (pin 7): this output is an open collector logic stage which requires a pull-up resistor, r l , to v cc for proper operation. it can sink 5ma of load current. when decoding fsk signals, fsk data output is at ahigho or aoffo state for low input frequency, and at alowo or aono state for high input frequency. if no input signal is present, the logic state at pin 7 is indeterminate. fsk comparator input (pin 8): this is the high impedance input to the fsk voltage comparator. normally, an fsk post-detection or data filter is connected between this terminal and the pll phase detector output (pin 11). this data filter is formed by r f and c f (see figure 3. ) the threshold voltage of the comparator is set by the internal reference voltage, v ref , available at pin 10. reference voltage, v ref (pin 10): this pin is internally biased at the reference voltage level, v ref : v ref = v cc /2 - 650mv. the dc voltage level at this pin forms an internal reference for the voltage levels at pins 5, 8, 11 and 12. pin 10 must be bypassed to ground with a 0.1 f capacitor for proper operation of the circuit. loop phase detector output (pin 11): this terminal provides a high impedance output for the loop phase detector. the pll loop filter is formed by r 1 and c 1 connected to pin 11 (see figure 3. ) with no input signal, or with no phase error within the pll, the dc level at pin 11 is very nearly equal to v ref . the peak to peak voltage swing available at the phase detector output is equal to 2 x v ref . vco control input (pin 12): vco free-running frequency is determined by external timing resistor, r 0 , connected from this terminal to ground. the vco free-running frequency, f o , is: f o 1 r 0 c 0 hz where c 0 is the timing capacitor across pins 13 and 14. for optimum temperature stability, r 0 must be in the range of 10k to 100k (see figure 9. ) this terminal is a low impedance point, and is internally biased at a dc level equal to v ref . the maximum timing current drawn from pin 12 must be limited to < 3ma for proper operation of the circuit. vco timing capacitor (pins 13 and 14): vco frequency is inversely proportional to the external timing capacitor, c 0 , connected across these terminals (see figure 6. ) c 0 must be non-polar, and in the range of 200pf to 10 f. vco frequency adjustment: vco can be fine-tuned by connecting a potentiometer, r x , in series with r 0 at pin 12 (see figure 10. ) vco free-running frequency, f o : xr-2211 does not have a separate vco output terminal. instead, the vco outputs are internally connected to the phase detector sections of the circuit. for set-up or adjustment purposes, the vco free-running frequency can be tuned by using the generalized circuit in figure 3 , and applying an alternating bit pattern of o's and 1's at the known mark and space frequencies. by adjusting r 0 , the vco can then be tuned to obtain a 50% duty cycle on the fsk output (pin 7). this will ensure that the vco f o value is accurately referenced to the mark and space frequencies.
xr-2211 7 rev. 3.01 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? loop filter ??? ??? ??? ?? ?? ?? ??? ??? fsk output fsk comp data filter det ?? ?? ?? ??? lock detect outputs lock detect comp det vco lock detect filter preamp input f f v cc r l r b loop phase detect c 1 11 r 1 r f c f 8 fsk comp. 7 internal reference 6 ldoq 10 lock detect comp. vco 14 13 12 r 0 c 0 2 0.1 f input signal quad phase detect r d 3 c d 5 ldoqn figure 2. functional block diagram of a tone and fsk decoding system using xr-2211 f f 0.1 f figure 3. generalized circuit connection for fsk and tone detection + +
xr-2211 8 rev. 3.01 design equations (all resistance in , all frequency in hz and all capacitance in farads, unless otherwise specified) (see figure 3 for definition of components) 1. vco center frequency, f o : f o 1 r 0 c 0 2. internal reference voltage, v ref (measured at pin 10): v ref v cc 2 650 mv in volts 3. loop low-pass filter time constant, : c 1 r pp ( seconds ) where: r pp r 1 r f r 1 r f if r f is or c f reactance is , then r pp = r1 4. loop damping, : 1250 c 0 r 1 c 1 note: for derivation/explanation of this equation, please see tan-011. 5. loop-tracking bandwidth, f f 0 f f 0 r 0 r 1 tracking bandwidth f f f ll f 1 f 2 f o f lh
xr-2211 9 rev. 3.01 6. fsk data filter time constant, tf: f r b r f ( r b r f ) c f ( seconds ) 7. loop phase detector conversion gain, kd: (kd is the differential dc voltage across pin 10 and pin11, per unit of phase error at phase detector input): k d v ref r 1 10, 000 volt radian note: for derivation/explanation of this equation, please see tan-011. 8. vco conversion gain, ko: (ko is the amount of change in vco frequency, per unit of dc voltage change at pin 11): k 0 2 v ref c 0 r 1 radian second volt 9. the filter transfer function: f ( s ) 1 1 sr 1 c 1 at 0 hz . s = j and = 0 10. total loop gain. k t : k t k o k d f ( s ) r f 5, 000 c 0 ( r 1 r f ) 1 seconds 11. peak detector current i a : i a v ref 20, 000 ( v ref in volts and i a in amps ) note: for derivation/explanation of this equation, please see tan-011.
xr-2211 10 rev. 3.01 applications information fsk decoding figure 10 shows the basic circuit connection for fsk decoding. with reference to figure 3 and figure 10 , the functions of external components are defined as follows: r 0 and c 0 set the pll center frequency, r 1 sets the system bandwidth, and c 1 sets the loop filter time constant and the loop damping factor. c f and r f form a one-pole post-detection filter for the fsk data output. the resistor r b from pin 7 to pin 8 introduces positive feedback across the fsk comparator to facilitate rapid transition between output logic states. design instructions: the circuit of figure 10 can be tailored for any fsk decoding application by the choice of five key circuit components: r 0 , r 1 , c 0 , c 1 and c f . for a given set of fsk mark and space frequencies, f o and f 1 , these parameters can be calculated as follows: (all resistance in 's, all frequency in hz and all capacitance in farads, unless otherwise specified) a) calculate pll center frequency, f o : f o f 1 f 2 b) choose value of timing resistor r 0 , to be in the range of 10k to 100k . this choice is arbitrary. the recommended value is r 0 = 20k . the final value of r 0 is normally fine-tuned with the series potentiometer, r x . r o r o r x 2 c) calculate value of c0 from design equation (1) or from figure 7 : c o 1 r 0 f 0 d) calculate r1 to give the desired tracking bandwidth (see design equation 5). r 1 r 0 f 0 ( f 1 f 2 ) 2 e) calculate c1 to set loop damping. (see design equation 4): normally, = 0.5 is recommended. c 1 1250 c 0 r 1 2
xr-2211 11 rev. 3.01 f) the input to the xr-2211 may sometimes be too sensitive to noise conditions on the input line. figure 4 illustrates a method of de-sensitizing the xr-2211 from such noisy line conditions by the use of a resistor, rx, connected from pin 2 to ground. the value of rx is chosen by the equation and the desired minimum signal threshold level. v in minimum ( peak ) v a v b v 2.8 mv offset v ref 20, 000 (20, 000 r x ) or r x 20, 000 v ref v 1 v in minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting v threshold) ?? ?? ?? v cc rx input 2 20k va 20k to phase detector vb v ref 10 figure 4. desensitizing input stage g) calculate data filter capacitance, c f : r sum ( r f r 1 ) r b ( r 1 r f r b ) c f 0.25 ( r sum baud rate ) baud rate in 1 seconds note: all values except r 0 can be rounded to nearest standard value.
xr-2211 12 rev. 3.01 4 6 8 1012 14 1618 202224 1 2 3 4 5 5 2 4 3 1 1 2 3 4 5 curve r 0 5k 10k 30k 100k 300k v+ (volts) f o = 1khz r f = 10r 0 normalized frequency drift (% of f ) r (k ) = 1 khz r 0 =5k w figure 5. typical supply current vs. v+ (logic outputs open circuited) figure 6. vco frequency vs. timing resistor figure 7. vco frequency vs. timing capacitor figure 8. typical f o vs. power supply characteristics figure 9. typical center frequency drift vs. temperature 20 15 10 5 0 r 0 =10k w r 0 >100k 4681012141618202224 ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? 1.0 0.1 0.01 100 1000 10000 f o (hz) +1.0 +0.5 0 -0.5 -1.0 -50 -25 0 25 50 75 100 125 temperature ( c) r 0 =1m w r 0 =500k r 0 =50k r 0 =10k 1m w 500k 50k 10k v+ = 12v r 1 = 10 r 0 f o supply voltage, v + (volts) r 0 =20k ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? 1,000 100 10 0 1000 10000 f o (hz) 1.02 1.01 1.00 0.99 0.98 0.97 r 0 =5k c 0 =0.001 f c 0 =0.0033 f c 0 =0.01 f c 0 =0.0331 f c 0 =0.1 f c 0 =0.33 f r 0 =160k r 0 =40k r 0 =80k r 0 =10k 0 normalized frequency o supply vs. current (ma) c ( f) 0
xr-2211 13 rev. 3.01 design example: 1200 baud fsk demodulator with mark and space frequencies of 1200/2200. step 1: calculate f o : from design instructions ( a ) f o 12002200 =1624 step 2: calculate r 0 : r 0 =10k with a potentiometer of 10k. (see design instructions (b)) ( b ) r t 10 10 2 15 k step 3: calculate c 0 from design instructions ( c ) c o 1 150001624 39 nf step 4: calculate r 1 : from design instructions ( d ) r 1 2000016242 ( 2200 1200 ) 51, 000 step 5: calculate c 1 : from design instructions ( e ) c 1 125039 nf 510000.5 2 3.9 nf step 6: calculate r f : r f should be at least five times r 1 , r f = 51,000 ? 5 = 255 k step 7: calculate r b : r b should be at least five times r f , r b = 255,000 ? 5 = 1.2 m step 8: calculate r sum : r sum ( r f r 1 ) r b ( r f r 1 r b ) 240 k step 9: calculate c f : c f 0.25 r sum baud rate 1 nf note: all values except r 0 can be rounded to nearest standard value.
xr-2211 14 rev. 3.01 v cc r l 5.1k 5% r b 1.8m 5% loop phase detect 11 c 1 2.7nf 5% r 1 35.2k 1% 8 fsk comp. r f 178k 5% c f 1nf 10% 7 data output internal reference 0.1 m f 10 vco 14 13 12 rx 20k r 0 20k 1% c o 27nf 5% 2 0.1 m f input signal lock detect comp. vco tune fine 6 ldoq 5 ldoqn quad phase detect figure 10. circuit connection for fsk decoding of caller identification signals (bell 202 format) v cc r l 5.1k r b loop phase detect c 1 11 r 1 r f c f 8 fsk comp. 7 internal reference 0.1 m f 10 vco 14 13 12 r 0 c 0 rx 2 0.1 m f input signal lock detect comp. 6 ldoq 5 ldoqn 3 c d r d between 400k and 600k quad phase detect figure 11. external connectors for fsk demodulation with carrier detect capability + +
xr-2211 15 rev. 3.01 loop phase detect 11 c 1 220pf 5% r 1 200k 1% 8 fsk comp. v cc 7 internal reference 0.1 m f 10 vco 14 13 12 r 0 20k 1% c 0 50nf 5% rx 5k 2 0.1 m f input tone lock detect comp. tune fine 6 ldoq rl2 5.1k rl3 5.1k logic output 5 ldoqn 3 c d 80nf r d 470k quad phase detect figure 12. circuit connection for tone detection v cc vco + + fsk decoding with carrier detect the lock detect section of xr-2211 can be used as a carrier detect option for fsk decoding. the recommended circuit connection for this application is shown in figure 11. the open collector lock detect output, pin 6, is shorted to data output (pin 7). thus, data output will be disabled at alowo state, until there is a carrier within the detection band of the pll and the pin 6 output goes ahigho to enable the data output. note: data output is alowo when no carrier is present. the minimum value of the lock detect filter capacitance c d is inversely proportional to the capture range, + fc. this is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. it is further limited by c 1 . for most applications, fc > f/2. for r d = 470k , the approximate minimum value of c d can be determined by: c d 16 f c in f and f in hz. c in f and f in hz. with values of c d that are too small, chatter can be observed on the lock detect output as an incoming signal frequency approaches the capture bandwidth. excessively large values of c d will slow the response time of the lock detect output. for caller i.d. applications choose c d = 0.1 f. tone detection figure 12 shows the generalized circuit connection for tone detection. the logic outputs, ldoqn and ldoq at pins 5 and 6 are normally at ahigho and alowo logic states, respectively. when a tone is present within the detection band of the pll, the logic state at these outputs become reversed for the duration of the input tone. each logic output can sink 5ma of load current. both outputs at pins 5 and 6 are open collector type stages, and require external pull-up resistors r l2 and r l3 , as shown in figure 12. with reference to figure 3 and figure 12 , the functions of the external circuit components can be explained as follows: r 0 and c 0 set vco center frequency; r 1 sets the detection bandwidth; c 1 sets the low pass-loop filter time constant and the loop damping factor.
xr-2211 16 rev. 3.01 design instructions: the circuit of figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components: r 0 , r 1 , c 0 , c 1 and c d . for a given input, the tone frequency, f s , these parameters are calculated as follows: (all resistance in 's, all frequency in hz and all capacitance in farads, unless otherwise specified) a) choose value of timing resistor r 0 to be in the range of 10k to 50k . this choice is dictated by the max./min. current that the internal voltage reference can deliver. the recommended value is r 0 = 20k . the final value of r 0 is normally fine-tuned with the series potentiometer, r x . b) calculate value of c 0 from design equation (1) or from figure 7 f s = f o : c o 1 r 0 fs c) calculate r 1 to set the bandwidth + f (see design equation 5): r 1 r 0 f 0 2 f note: the total detection bandwidth covers the frequency range of f o + f d) calculate value of c 1 for a given loop damping factor: normally, = 0.5 is recommended. c 1 1250 c 0 r 1 2 increasing c 1 improves the out-of-band signal rejection, but increases the pll capture time. e) calculate value of the filter capacitor c d . to avoid chatter at the logic output, with r d = 470k , c d must be: c d 16 f cin f increasing c d slows down the logic output response time. design examples: tone detector with a detection band of + 100hz: a) choose value of timing resistor r 0 to be in the range of 10k to 50k . this choice is dictated by the max./min. current that the internal voltage reference can deliver. the recommended value is r 0 = 20 k . the final value of r 0 is normally fine-tuned with the series potentiometer, r x . b) calculate value of c 0 from design equation (1) or from figure 6 f s = f o : c 0 1 r 0 f s 1 20, 0001, 000 50 nf
xr-2211 17 rev. 3.01 c) calculate r 1 to set the bandwidth + f (see design equation 5): r 1 r 0 f o 2 f 20, 0001, 0002 100 400 k note: the total detection bandwidth covers the frequency range of f o + f d) calculate value of c 0 for a given loop damping factor: normally, = 0.5 is recommended. c 1 1250 c 0 r 1 2 12505010 9 400, 0000.5 2 6.25 pf increasing c 1 improves the out-of-band signal rejection, but increases the pll capture time. e) calculate value of the filter capacitor c d . to avoid chatter at the logic output, with r d = 470k , c d must be: c d 16 f 16 200 80 nf increasing c d slows down the logic output response time. f) fine tune center frequency with 5k potentiometer, r x . 0.1 m f r f 100k v cc loop phase detect c 1 11 r 1 8 fsk comp . 7 3 2 1 4 11 lm324 c f output demodulated internal reference 6 ldoq 0.1 m f 10 lock detect comp. vco 14 13 12 r 0 c 0 2 0.1 m f input fm quad phase detect 5 ldoqn figure 13. linear fm detector using xr-2211 and an external op amp. (see section on design equation for component values.) v cc + + +
xr-2211 18 rev. 3.01 linear fm detection xr-2211 can be used as a linear fm detector for a wide range of analog communications and telemetry applications. the recommended circuit connection for this application is shown in figure 13. the demodulated output is taken from the loop phase detector output (pin 11), through a post-detection filter made up of r f and c f , and an external buffer amplifier. this buffer amplifier is necessary because of the high impedance output at pin 11. normally, a non-inverting unity gain op amp can be used as a buffer amplifier, as shown in figure 13. the fm detector gain, i.e., the output voltage change per unit of fm deviation can be given as: v out r 1 v ref 100 r 0 where vr is the internal reference voltage (v ref = v cc /2 - 650mv). for the choice of external components r 1 , r 0 , c d , c 1 and c f , see the section on design equations. capacitor 6 input 5 7 resistor v + figure 14. equivalent schematic diagram 20k 20k internal voltage reference input preamplifier and limiter 10k 10k quadrature phase detector lock detect filter lock detect outputs lock detect comparator fsk data output fsk comparator input loop detector output a from vco 2k a' loop phase detector 8k 12 r 0 timing 13 b b' c 0 14 voltage controlled oscillator ref voltage output 10 2 b from vco b' 3 2k a 1 4 ground fsk comparator 8 11 a' timing
xr-2211 19 rev. 3.01 a 0.100 0.200 2.54 5.08 a 1 0.015 0.060 0.38 1.52 b 0.014 0.026 0.36 0.66 b 1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 d 0.685 0.785 17.40 19.94 e 1 0.250 0.310 6.35 7.87 e 0.300 bsc 7.62 bsc e 0.100 bsc 2.54 bsc l 0.125 0.200 3.18 5.08 a 0 15 0 15 l d b e b 1 14 lead ceramic dual-in-line (300 mil cdip) rev. 1.00 symbol min max min max inches millimeters a 1 a c seating plane base plane a 14 17 8 e 1 e note: the control dimension is the inch column
xr-2211 20 rev. 3.01 14 lead plastic dual-in-line (300 mil pdip) rev. 1.00 14 1 8 7 d e b 1 a 1 e 1 e a l b seating plane symbol min max min max inches a 0.145 0.210 3.68 5.33 a 1 0.015 0.070 0.38 1.78 a 2 0.115 0.195 2.92 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 0.725 0.795 18.42 20.19 e 0.300 0.325 7.62 8.26 e 1 0.240 0.280 6.10 7.11 e 0.100 bsc 2.54 bsc e a 0.300 bsc 7.62 bsc e b 0.310 0.430 7.87 10.92 l 0.115 0.160 2.92 4.06 a 0 15 0 15 millimeters a a 2 c note: the control dimension is the inch column e b e a
xr-2211 21 rev. 3.01 symbol min max min max a 0.053 0.069 1.35 1.75 a 1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 d 0.337 0.344 8.55 8.75 e 0.150 0.157 3.80 4.00 e 0.050 bsc 1.27 bsc h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 a 0 8 0 8 inches millimeters 14 lead small outline (150 mil jedec soic) rev. 1.00 e 14 8 7 d e h b a l c a 1 seating plane a note: the control dimension is the millimeter column 1
xr-2211 22 rev. 3.01 notes
xr-2211 23 rev. 3.01 notes
xr-2211 24 rev. 3.01 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1995 exar corporation datasheet june 1997 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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